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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Features
* fractional or integer Modes * 14 Ghz, 16-Bit rf n-counter * 24-Bit step size resolution, 6 hz typ * Ultra Low Phase noise 12 Ghz, 50 Mhz ref. -98 / -103 dBc/hz @ 20 khz (frac / integer) * reference Path input: 200 Mhz * 14-Bit reference Path Divider * Low fractional spurious * reference spurs: -90 dBc typ * auto and triggered sweeper functions * cycle slip Prevention (csP) for fast settling * autotune support for external step tuned Vcos * Multi-Vco support * auxiliary clock source * 40 Lead 6x6mm sMt Package: 36mm
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PLL - fractionaL-n synthesizer - sMt
Typical Applications
* Base stations for Mobile radio (GsM, Pcs, Dcs, cDMa, WcDMa) * Wireless Lans, WiMax * communications test equipment * catV equipment * fMcW sensors * automotive radar * Phased-array systems
Functional Diagram
(Figure 1.)
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For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
General Description
the hMc702LP6ce is a siGe BicMos fractional-n frequency synthesizer. the synthesizer includes a 8Ghz 16-bit rf n-Divider, a 24-bit delta-sigma modulator, a very low noise digital phase frequency detector (PfD), and a precision controlled charge pump. in addition the synthesizer supports an external step tuned Vco. the fractional synthesizer features an advanced delta-sigma modulator design that allows ultra-fine frequency step sizes. the synthesizer features the ability to alter both the phase-frequency detector (PfD) gain and the cycle slipping characteristics of the PfD. this feature can reduce the time to arrive at the new frequency by 50% vs. conventional PfDs. Ultra low in-close phase noise also allows wider loop bandwidths for faster frequency hopping. the synthesizer contains a built-in linear sweeper function, which allows it to perform frequency chirps with a wide variety of sweep times, polarities and dwells, all with an external or automatic sweep trigger. a General Purpose output (GPo) bus supports the use of multiple Vcos. in addition the synthesizer has a number of auxiliary clock generation modes that can be accessed via the GPo.
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PLL - fractionaL-n synthesizer - sMt
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Vcchf = VccPrs = rVDD = +3.3V VPPcP = Vccoa = VDDPDr = VPPDrV = VDDPD = VDDPDV = +5V DVDD = DVDDio = DVDDQ = +3.3V GnDDrV = GnDcP = GnDPD = GnDPDV = GnDPDr = 0V
Electrical Specifications, TA = +25C
Table 1. Electrical Specifications
Parameter Prescaler Characteristics Max rf input frequency (3.3V) Max rf input frequency (2.7 - 3.3V) Min rf input frequency rf input Power 16-bit n-Divider range (integer) 16-bit n-Divider range (fractional) REF Input Characteristics Max ref input frequency (pin XrefP) Max ref input frequency (pin Xsin) Max ref frequency with autocal Min ref input frequency ref input Voltage range (pin XrefP) ref input Power range (pin Xsin) ref input capacitance ac coupled 50 source 1.5 -6 200 200 220 220 60 100 2.0 0 3.3 12 5 Mhz Mhz Mhz khz mVpp dBm pf fmin10 Ghz 16-Bit divider and fixed divide-by-2 step of 2 fraction nominal Divide ratio varies (-6 / +8) dynamically max -10 0 64 72 -6 12 12 14 13 0.1 10 Ghz Ghz Mhz dBm conditions / notes Min typ Max Units
131,070 131,062
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 1. Electrical Specifications
Parameter 14-Bit r-Divider range Phase Detector fractional Mode Max Phase Detector frequency Min Phase Detector frequency integer Mode Max Phase Detector frequency Min Phase Detector frequency Charge Pump
(Continued)
conditions / notes Min 1 typ Max 16,383 Units
70
75 100
Mhz khz
110
150 100
Mhz khz
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PLL - fractionaL-n synthesizer - sMt
Max output current Min output current charge Pump Gain step size (5-bits) charge Pump trim step size (3-bits) charge Pump offset step size (4-bits) PfD / charge Pump noise (integer) 1 khz 10 khz 100 khz Less than 3 dB degradation typ. at these limits compliance Voltage -406 a offset -406 a offset Logic Inputs Vih input high Voltage ViL input Low Voltage Logic Outputs Vih output high Voltage ViL output Low Voltage Power Supply Voltages Vcc - analog 3V supplies DVDD - Digital internal supply DVDDio - Digital i/o supply analog 5V supplies VccPrs, rVDD, Vcchf DVDD, DVDDQ DVDDio Vccoa, VPPcP, VPPDrV, VDDPD, VDDPDV, VDDPDr 3 3 1.8 4.5 VDDio-0.1 VDDio-0.4 0.4 0.8 6 Ghz, 50 Mhz ref, input referred
4 125 125 14 29
ma a a a a
-141 -149 -155
dBc/hz dBc/hz dBc/hz
VPPcP-0.8 VPPcP-0.4
V V
V 0.4 V
V 0.1 V
3.3 3.3 3.3 5.0
3.45 3.45 5.5 5.5
V V V V
Power Supply Current (6 Ghz fractional Mode, 50 Mhz PfD) analog +5V analog +3.3V Digital +3.3V Power Down - crystal off Vccoa, VPPcP, VPPDrV, VDDPD, VDDPDV, VDDPDr VccPrs, rVDD, Vcchf DVDD, DVDDio, DVDDQ reg 01h = 0 crystal not clocked 26 116 19 10 ma ma ma a
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 1. Electrical Specifications
Parameter Power Down - crystal on, 100 Mhz Temperature Sensor (3-bit) Min temperature Max temperature temp change / LsB Worst case absolute temp error current consumption (when enabled) Power on Reset typical reset Voltage on DVDD Min DVDD Voltage for no reset Closed Loop Phase Noise 12 Ghz Vco, integer, 100 Mhz PfD 12 Ghz Vco, integer, 100 Mhz PfD 12 Ghz Vco, integer, 100 Mhz PfD 12 Ghz Vco, fractional, 50 Mhz PfD 12 Ghz Vco, fractional, 50 Mhz PfD 12 Ghz Vco, fractional, 50 Mhz PfD Closed Loop Phase Noise integer Mode fractional Mode
(Continued)
conditions / notes reg 01h = 0 crystal clocked 100 Mhz Min typ 20 Max 200 Units a
readout: 000 readout: 111
-32 +82 17.5 10 2
c c c/LsB c ma
700 1.5
mV V
1 khz offset 10 khz offset 100 khz offset 1 khz offset 10 khz offset 100 khz offset normalized to 1 hz Measured with 50 Mhz PfD Measured with 50 Mhz PfD
-96 -105 -111 -92 -98 -103
dBc/hz dBc/hz dBc/hz dBc/hz dBc/hz dBc/hz
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PLL - fractionaL-n synthesizer - sMt
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-227 -221
dBc/hz dBc/hz
Table 2. Absolute Maximum Ratings
Parameter rVDD, Vcchf, DVDD, DVDDQ, VccPrs Vccoa, VPPcP, VPPDrV, VDDPD, VDDPDV, VDDPDr, DVDDio operating temperature storage temperature Maximum Junction temperature reflow soldering Peak temperature time at Peak temperature esD sensitivity (hBM) 260 c 40 sec class 1B Rating -0.3 to +3.6V -0.3 to +6V -40 to +85 c -65 to +120 c +150 c
stresses above those listed under absolute Maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 3. Pin Description
Pin no. 1 2 3 4 5 6 7 8 9 Pin name VccPrs Vccoa VPPcP cP GnDcP GnDDrV VPPDrV VDDPD GnDPD n/c VDDPDV GnDPDV VDDPDr GnDPDr XrefP rVDD Xsin refcaP rstB DVDD GPo1 GPo2 GPo3 sen sDi scK VsLe VsDo VscK LD_sDo DVDDio DVDD GnDhf Vcoin GnDhf Vcchf Bias Pin type supply supply supply analog o/P GnD GnD supply supply GnD n/c supply GnD supply GnD analog i/P supply analog i/P analog i/o cMos i/P supply Do Do Dio cMos i/P cMos i/P cMos i/P cMos o/P cMos o/P cMos o/P cMos o/P supply supply GnD rf i/P GnD supply analog i/P Description rf Prescaler Power supply. nominally +3.3V chargePump opamp Power supply. nominally +5V Power supply for charge Pump. nominally +5V charge Pump output Power supply GnD for charge Pump charge Pump GnD Power supply for charge Pump, nominally +5V Power supply for Phase Detectors, nominally +5V Power supply GnD for Phase Detector no connection Power supply for Phase Detector Vco Path, nominally +5V Power supply GnD for Phase Detector Vco Path Power supply for Phase Detector ref Path, nominally +5V Power supply GnD for Phase Detector ref Path square Wave crystal ref input Power supply for ref Path, nominally +3.3V sinusoidal crystal reference input reference Path bypass reset input (active low) Digital Power supply, nominally +3.3V General Purpose output 1 with tristate General Purpose output 2 with tristate General Purpose input/output with tristate may be configured for external ramp trigger input. see register reG 14h[5] Main serial port enable input Main serial port data input Main serial port clock input Vco serial port enable output Vco serial port data output Vco serial port clock output Lock Detect or Main serial Port Data output Power supply for digital i/o, matches external Digital supply in 1.8V to 5.5V range internal Digital Power supply. nominally 3.3V Ground for rf input to the rf prescaler Ground for rf input rf section Power supply. nominally 3.3V Decoupling Pin for rf section, nominally external 1nf bypassed to Vcchf
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PLL - fractionaL-n synthesizer - sMt
10, 20, 21, 26 11 12 13 14 15 16 17 18 19 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Figure 2. Figure 1.
Typical Phase Noise
-60 -70 -80 -90 PHASE NOISE (dBc/Hz) -100 -110 -120 -130 -140 -150 -160 -170 -180 100 1000 10
4
Typical Phase Noise @ 30 kHz Offset Fractional Mode
-96 -98 PHASE NOISE (dBc/Hz) -100 -102 -104 -106 -108 -110 4000 HMC588LC4B VCO HMC587LC4B VCO HMC508LP5E VCO HMC513LP5E VCO HMC529LP5E VCO
FRAC MODE 12GHz, 50MHz PFD with HMC582 VCO Typ FOM -221dBc
INTEGER MODE 13GHz, 100MHz PFD with HMC584 VCO Typ FOM -228 dBc
HMC515LP5E VCO
HMC586LC4B VCO 6000 8000 10000 12000 14000
10
5
10
6
10
7
10
8
FREQUENCY (Hz)
OUTPUT FREQUENCY (MHz)
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PLL - fractionaL-n synthesizer - sMt
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Figure 3.
Figure 4.
RF Divider Sensitivity
10 0
Frequency Sweep
6150 6100 FREQUENCY (MHz)
6050
Sensitivity (dBm)
-10
6000
-20
5950
-30
5900
-40
0
2000
4000
6000
8000
10000
12000
14000
5850 -2 -1 0 1 TIME (ms) 2 3
FREQUENCY (MHz)
Figure 5.
Figure 6.
Cycle Slip Prevention: Frequency Hop from 5200 MHz to 3950 MHz
5300 5100
Typical Max Frequency vs. Temperature -6 dBm, 3.3V
-60 30kHz Offset, +85C Divider Failure +85C -70 30kHz Offset, -40C Divider Failure +25C Divider Failure -40C 15500 30kHz Offset, +25C
FREQUENCY (MHz)
PHASE NOISE (dBc/Hz) 40 50 60 70
4900 4700 4500 4300 4100 3900 -10 CSP ON CSP OFF
-80
-90
-100
0
10
20
30 TIME (us)
-110 13000
13500
14000
14500
15000
FREQUENCY (MHz)
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Theory of Operation
the hMc702LP6ce synthesizer consists of the following functional blocks 1. reference Path input Buffers 2. reference Path Divider 3. Vco Path input Buffer 4. Vco Path Multi-Modulus Prescaler/Divider 5. fractional Modulator 6. Phase frequency Detector 7. charge Pump 8. Main serial Port each of these blocks is described briefly in the following section. 9. Vco serial Port for stepped Vco support 10. temperature sensor 11. Power on reset circuit 12. Vco autocalibration subsystem 13. cW sweeper subsystem 14. auxiliary clock Generator 15. General Purpose output (GPo) Bus 16. Multiple Vco controller
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PLL - fractionaL-n synthesizer - sMt
Reference Path
the full reference Path block diagram is shown in figure 7. the ultra low noise phase detector requires the best possible reference signal. since a given application may desire to use a square wave or a 50 ohm sinusoidal crystal source, hMc702LP6ce offers two input ports, each one optimized for the lowest possible noise for the source type being used. for absolute best low noise performance, the sine wave path should be used. the user should use only one ref path input, that is the input that matches their reference source type. note the input is defaulted to the square wave input on power up. should the sine reference path be used, it is necessary to enable the sine input, shut down the square wave input and set the mux (rfp_buf_sin_en=1, rfp_buf_sq_en=0, rfp_buf_sin_sel=1, table 12). the unused port should be left open. the reference path supports input frequencies of up to 200 Mhz typical, however the maximum frequency at the phase detector (PfD) depends upon the mode of operation, worst case at +85c, 70 Mhz in fractional mode and 110 Mhz in integer mode. hence reference inputs of greater than the PfD maximum frequency must use the appropriate r divider setting. a further restriction exists. if the Vco auto calibration feature is used, the reference input must not exceed 60 Mhz.
Figure 7. Reference Sine Input Stages the unused reference port is normally not connected.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Sine Reference Input
the crystal reference sine input stage is shown in figure 8. this is the lowest noise reference path. this is a common emitter single ended bipolar buffer. the Xsin input pin is Dc coupled and has about 950 mV bias on it. expected input is a 0 dBm sinusoid from a 50 ohm source. normally the input should be ac coupled externally. the sine buffer input impedance is dominated by a 25 ohm shunt resistor in series with a 50 pf on chip cap. should a lower input impedance be needed, an external 50 ohm shunt resistor can be used, Dc isolated by an external bypass cap. the sine input reference path phase noise floor is approximately equivalent to -159 dBc/hz. for best performance care should be taken to provide a crystal reference source with equivalent or better phase noise floor.
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PLL - fractionaL-n synthesizer - sMt
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Figure 8. Ref Sine Input
Square Wave Reference Input
the square wave ref input stage is shown in figure 9. the stage is designed to accept square wave inputs from cML to cMos levels. slightly degraded phase noise performance may be obtained with quasi sine 1 Vpp inputs. it may be necessary to attenuate very large cMos levels if absolute best in close phase noise performance is required. input reference should have a noise floor better than -160 dBc/hz to avoid degradation of the input reference path.
Figure 9. Square Wave Ref Input Stage
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Reference Path 'R' Divider
the referenced path features a 14-bit divider (rfp_div_ratio, Reg03h<13:0> table 14) and can divide input signals at up to 200 Mhz by numbers from 1 to 16,383. the selected input reference source may be divided or bypassed (rfp_div_select), and applied to the phase detector reference input.
VCO Auto Tuning and Serial Port Clocks
the optional Vco auto tuning state machine and the Vco serial Port clocks use the undivided selected external reference signal, as determined by rfp_xref_sin_select Reg12h<6> (table 29), and as shown in figure 10.
Reference Path Test Features
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PLL - fractionaL-n synthesizer - sMt
a fractional synthesizer is a complex combination of a low phase noise analog oscillator running in close proximity with a nearly randomly modulated delta-sigma digital modulator. clean spur free operation of the synthesizer requires proper board layout of power and grounds. spurious sources are often difficult to identify and may be related to harmonics of the digital modulation which land near the operating frequency of the Vco, or they may arise from repeating patterns in the digital modulation itself . the loop filter and the fractional modulator are designed to suppress these fractional spurs, but it is sometimes the case that the isolation of the spurious products comes from layout issues. the problem is how to identify the sources of spurious products if they occur? the reference path of the hMc702LP6ce features some interesting test options for clocking the digital portion of the synthesizer which may provide for a better understanding of the source of reference spurs should they occur. see figure 10, table 12 and table 29 for more register details. it is possible for example to set the synthesizer to integer mode of operation, where the digital harmonics normally fall directly on the Vco frequency. We might chose for example to use the sine source (rfp_buf_sine_sel=1, div_ todig_en=0) to drive the reference divider. in such a case the delta sigma modulator is not normally used, however if we wish to test the effects of the digital power supply isolation, we could input a 2nd reference source on the square wave input, enable its buffer (rfp_buf_sq_en=1), and enable the 2nd crystal to clock the unused delta sigma modulator (sqr_todig_en=1 and dsm_xref_sin_select=0). this would allow the square wave clock to be set independently of the locked integer mode Vco, and hence measure the coupling of the digital to the sidebands of the Vco at various frequencies. such a test can help in identifying and debugging grounding and layout issues in the application circuit related to the digital portion of the PcB should they occur. in general it is recommended to follow the suggested layout closely to avoid any such problems.
Figure 10. Reference Path Block Diagram
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
VCO Path
the rf path from the Vco to the phase detector, is referred to as the Vco path. the Vco path consists of an input isolation buffer and a multi-modulus prescaler, or simply the n divider. the n divider is controlled by the fractional modulator. this path operates with inputs directly from the external Vco.
RF Input Stage
the synthesizer rf input stage routes the external Vco to the phase detector via a 16-bit fractional divider. the rf input path is rated to operate nominally from 100 khz to 13 Ghz in fractional and 14 Ghz in integer modes. the rf input stage also provides isolation between the Vco and the prescaler. the rf input stage is a differential common emitter stage, Dc coupled for maximum flexibility. the input is protected by esD diodes as shown in figure 11. normally the rf input is ac coupled to a single ended external source. the rfinP buffer is well matched from a single ended 50 ohm source above about 3.5 Ghz, with the complimentary input grounded. if a better match is required at low frequency a simple shunt 50 ohm resistor can be used external to the package. if a differential external source is used then the two input pins may be used for best performance.
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PLL - fractionaL-n synthesizer - sMt
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Figure 11. RF Input Stage
RF Path 'N' Divider
the main rf path divider including a fixed divide-by-2, is capable of average divide ratios of even numbers between 131,062 and 72 in fractional mode, and 131,070 to 64 in integer mode. the reason for the difference between integer and fractional modes is that the fractional divider actually divides by up to 4 from the average divide number. actual division ratios when used with a given Vco will depend upon the reference frequency used and the desired output band.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
General Purpose Output (GPO) Interface
the hMc702LP6ce features a 3-wire General Purpose output (GPo) interface. GPo registers are described in Reg1Bh table 37. the GPo is a flexible interface that supports a number of different functions and real time waveform access including: a. General Data output from sPi register gpo_sel_0_ data (gpo_sel=0) b. Prescaler & reference path outputs (gpo_sel=1) c. Lock Detect Windows (gpo_sel=2) d. anti-cycle slip waveforms (gpo_sel=3) e. internal synchronized frac strobe with clocks (gposel=4) f. Mirror of Vco serial Port Data, clock, Latch enable (gposel=5) g. Modulator Phase accumulator (gposel=6) h. auxiliary oscillators (gposel=7) i. auto calibration Busy flag (gposel=8) j. Multiple Vco control, Latch enables (gposel=9) k. Modulator outputs (gposel=10)
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PLL - fractionaL-n synthesizer - sMt
General Data to GPO (gpo_sel=0)
setting register gpo_sel=0 in table 37 assigns the 3-bit data from register gpo_sel_0_data Reg1B<6:4> to the GPo bus.
Prescaler and Reference Path Outputs (gpo_sel = 1)
setting register gpo_sel=1 (Reg1B<3:0> table 37) results in the input crystal being buffered out to GPo3 as shown in figure 12. this is useful for example to generate a copy of the input crystal signal to drive other circuits in the application, while at the same time isolating the noisy circuits from the sensitive crystal output. often only the synthesizer requires very low phase noise from the crystal, hence it is desirable to isolate other circuits from the crystal itself and allow the synthesizer sole use of the low phase noise crystal. gpo_sel=1 also routes the 200 Mhz 14-bit reference path divider to GP02 and the 16-bit 14 Ghz Vco path prescaler output to GP01. this option allows the synthesizer to function as a stand alone fractional or integer prescaler and provides visibility into the prescaler and reference path timing for sensitive applications.
Figure 12. gpo_01 Outputs
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Lock Detect Windows (gpo_sel=2)
setting register gpo_sel = 2 (Reg1Bh<3:0> table 37) results in the lock detect window (figure 21) and the phase frequency detector UP and Dn output control signals (figure 24) to be routed to pins GPo1, GPo3 and GPo2 respectively. this option gives insight into the Lock Detection Process and could allow the synthesizer to be used with an external charge pump.
11
Figure 13. gpo_02 Outputs
Anti-cycle Slip Waveforms (gpo_sel = 3)
setting register gpo_sel=3 (Reg1Bh<3:0> table 37) gives visibility into the anti-cycle slipping function of the PfD as described in section Cycle Slip Prevention (csP). three waveforms, reference path freq > Vco path freq, vco path freq > ref path freq, and a PfD strobe which holds the PfD at maximum gain, are routed to GPo3, GPo2, and GPo1 respectively. these lines will be active during frequency pull-in and will indicate instantaneously which signal, reference or vco path is greater in frequency. the PfD strobe gives insight into when the PfD is near maximum gain at 2. the PfD strobe will be active until the Vco pulls into lock.
Internal Synchronized Frac strobe with clocks (gpo_sel= 4)
setting register gpo_sel=4 in (Reg1Bh<3:0> table 37) gives visibility into the internally synchronized strobe that is generated when commanding a frequency change by writing to the frac register. the internal strobe initiates the update to the fractional modulator, and the Vco sPi transfer if applicable. the internal frac strobe, the ref path divider output and the sine reference input are buffered out to GPo1,GPo2 and GPo3 respectively as shown in figure 14. in this mode, GPo1 may be used to trigger an external instrument = when doing frequency hopping tests for example.
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11 - 13
PLL - fractionaL-n synthesizer - sMt
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
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PLL - fractionaL-n synthesizer - sMt
Figure 14. gpo_04 Outputs
Mirror of VCO Port Data, Clock, Latch Enable (gpo_sel=5)
setting register gpo_sel=5 (reg1Bh <3:0> table 37) mirrors the output of the Vco sP on the gpo pins.
Modulator Phase Accumulator (gpo_sel=6)
setting register gpo_sel=6 (Reg1Bh<3:0> table 37) assigns the three msb's of the delta sigma modulator first accumulator to GPo<3:1> , where GPo3 is the msb. this feature provides insight into the phase of the Vco.
Auxiliary Oscillators (gpo_sel=7)
setting register gpo_sel=7 (Reg1Bh<3:0> table 37) assigns an auxiliary clock, an internal ring oscillator, and the internal sigma delta clock to GPo3, 2, 1 respectively. the control of the auxiliary clock is determined by reg18h table 34 and Reg19h table 35. in general terms, this highly flexible clock source allows the selection of one of the various Vco or crystal related clocks inside the synthesizer or the selection of a flexible unstabilized auxiliary ring oscillator clock. any of the sources may be routed out via gpo_sel=7. additional Reg18h table 34 clock controls allow the aux clock to be delayed by a variable amount (auxclk_modesel Reg18h<3:2>), or to be divided down by even values from 2 to 14 (auxclk_divsel Reg18h<6:4>).
Auto Calibration Busy Flag (gpo_sel=8)
setting register gpo_sel=8 (Reg1B<3:0> table 37) assigns a "vco calibration busy flag" to GPo1. this output will be high while the auto calibration is running.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Modulator Outputs (gpo_sel=10)
setting register gpo_sel=10 (Reg1B<3:0> table 37) assigns the three lsb's of the delta sigma modulator output to GPo<3:1>, where GPo1 is the lsb. this feature allows the possibility of using the hMc702LP6ce as a general purpose digital delta sigma modulator for many possible applications.
External VCO
the hMc702LP6ce is targeted for ultra low phase noise applications with an external Vco. the synthesizer has been designed to work with Vcos that can be tuned nominally over 0.5 to 4.5 Volts on the varactor tuning port with a +5V charge pump supply voltage. slightly wider ranges are possible with a +5.5V charge pump supply or with slightly degraded performance.
External VCO with Active Inverting OpAmp Loop Filter
an external opamp active filter is required to support external Vcos with tuning voltages above 5V. if an inverting opamp is used with a positive slope Vco, phase_sel reg05h <0> = 1 table 16 must be set to invert the PfD phase polarity and obtain correct closed loop operation.
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PLL - fractionaL-n synthesizer - sMt
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
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PLL - fractionaL-n synthesizer - sMt
Figure 15. Conventional Synthesizer with VCO
Step Tuned VCO Support
in addition to conventional varactor tuned Vcos, the hMc702LP6ce also supports step tuned type Vcos, as shown figure 16. a step tuned Vco allows the user to center the Vco on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the synthesizer charge pump. this helps to keep the tuning sensitivity more linear and reduces variations in kvco, which in turn minimizes variations in the closed loop bandwidth of the locked oscillator. Vcos with up to 6-bits of discrete digital tuning, and up to 10-bits of total control bits, are supported via a simple 3-wire Vco serial Port. if a step tuned Vco is used, the Vco switches are normally controlled automatically by the synthesizer using the auto tune feature. the Vco switches may also be controlled directly from register bits Reg0B<4:0> of spivco_direct_data, (Reg0Bh table 22) via direct serial port access for testing or for other special purpose operation. other control bits specific to the Vco may be output from Reg0B<9:5>.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Figure 16. Step Tuned VCO
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External VCO Control
the hMc702LP6ce is capable of controlling external Vcos that support additional features on the Vco serial port interface. Up to 10 data control bits may be written to an external Vco via Reg0Bh in table 22. for example such features as band selection or Vco power down may be supported in some Vcos.
Multiple VCO Control
hittite step tuned Vcos are directly addressable (see figure 31) and also supports the possibility of controlling multiple hMc step tuned Vcos by sharing the Vco serial Port lines as shown in figure 17.
Figure 17. Multiple VCO Control
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
VCO Tuning, Calibration & Temperature Correction
the hMc702LP6ce supports the use of an optional external step tuned Vco. a step tuned Vco allows the advantages of low phase noise associated with a low kvco, a consistent loop voltage on the tuning varactor from part to part, and lower charge pump voltages for a given range of Vco operation than would be possible with a conventional Vco with only varactor tuning. this feature also helps to reduce synthesizer charge pump non-linearity by keeping the output voltage of the charge pump as close as possible to the mid-rail condition.
Stepped Resonator VCO Calibration & Auto Tuning
in order to use a step tuned Vco in a closed loop, the Vco must be calibrated such that the synthesizer knows which switch position on the Vco is optimum for the desired output frequency. the hMc702LP6ce supports the automatic calibration of the step tuned Vco. the calibration fixes the Vco tuning voltage at the optimum mid-point of the charge pump output, then measures the free running Vco frequency on each switch setting and selects the setting which results in the free running output frequency that is closest to the desired phase locked frequency. this procedure results in a phase locked oscillator that locks over a very narrow voltage range on the varactor. the calibration can be run automatically every time that a change of frequency is desired. this ensures optimum selection of resonator settings vs. time and temperature. the accuracy desired in the calibration affects the amount of time required to calibrate the Vco. the calibration routine searches for the best step setting that locks the Vco at the current programmed frequency, while at a varactor voltage that is closest to mid-rail. if it is desirable to switch frequencies very quickly it is possible to eliminate the calibration time by calibrating the Vco in advance and storing the calibration information in the host. it will then be necessary for the host to run a routine that interrogates the Vco over the desired range of operation and records the optimum resonator switch settings for the desired frequency range. the calibration is then only run once on power up, and the settings stored in the host. the host must then program the switch settings directly when changing frequencies. frequency programming of the synthesizer by the host, including switch selection, can be done in the background, while the Vco is locked to the current frequency. the synthesizer normally writes the frequency control information to the Vco, via the Vco serial Port, upon receipt of a command that changes the PLL frequency, hence eliminating calibration delay from the locking time. a large change of frequency may require Main serial Port writes to: 1. the dsm_seed register (Reg 11h table 28), 2. Vco switch register spivco_direct_data (Reg0Bh table 22), 3. integer register dsm_intg (Reg0Fh table 26) and 4. the fractional register dsm_frac (Reg10h table 27). this last register triggers the frequency change in fractional mode. smaller steps in frequency may require fewer register writes. hence a maximum of 4 Main serial Port transfers to the synthesizer could be required to change frequencies. if the start phase of the fractional modulator is not of concern, then it is not necessary to write the dsm_seed register. similarly if the frequency step is small and the integer or the vco switch settings do not change, then these registers may also be left constant. in all cases, in fractional mode, it is necessary to write to the fractional register for frequency changes.
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PLL - fractionaL-n synthesizer - sMt
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For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Frequency Change & VCO AutoCal
the hMc702LP6ce will update the active registers described above only when a frequency change is requested. a. When in fractional mode (dsm_integer-mode Reg12h<3>=0) frequency change happens when the fractional register is written (Reg10h table 27). integer register may be written first and is buffered until the frac register is written. b. When in integer mode (dsm_integer-mode Reg12h<3>=1) frequency change happens when the integer register is written (Reg0Fh table 26). frac register is not used. c. if dsm_autoseed is enabled (Reg12h(7)=1), a frequency change updates the seed value of the fractional modulator digital phase accumulator (DPa) with the value from the seed register Reg11h table 28. d. if a step tuned Vco is used and auto tuning is enabled (Reg 0Ah(1)=1), then the frequency change will also initiate the Vco autotuning calibration. serial Port transfer to the Vco will happen automatically at the end of the autotuning procedure. the Vco will update its registers on the last clock tick of the VscK (see Vco serial Port Write operation). e. if a step tuned Vco is used and auto tuning is disabled (Reg 0Ah(1)=1), then the frequency change will also initiate the Vco serial Port transfer to the Vco. the Vco will update its registers with the value from spivco_ direct_data (Reg0Bh table 22) on the last clock tick of the VscK (see VCO Serial Port WRITE Operation). Buffering of the integer frequency value, seed value and vco tuning value allows the synthesizer and Vco to hold the current frequency while new values are written. the synthesizer prescaler will only change when a valid frequency change is written. if a step tuned Vco is used, and autotune is disabled, the Vco will be updated after the end of the Vco serial Port write cycle, about 16 clock cycles after the frequency change command.
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Step Tuned VCO AutoCal on Frequency Change
setting vcot_auto_start (Reg0Ah<0> table 21) will cause the switched resonator Vco calibration to start automatically whenever a frequency change is requested.
Step Tuned VCO Manual Calibration
setting vcot_man_start (Reg0Ah<1>=1 table 21) starts a switched resonator Vco calibration cycle for the current programmed frequency. dsm_auto_start (Reg0Ah<0>=0) must be cleared. the value of the current Vco switch setting determined by the calibration cycle is readable in the spivco_direct_data (Reg0Bh table 22) register.
Step Tuned VCO Calibration Time & Accuracy
if a switched resonator Vco, is used, it may be calibrated by searching for the nearest resonator switch position that yields the closest free running Vco frequency to the programmed frequency of the synthesizer. the measurement is done with the Vco open loop and the varactor tuning port forced to VPPcP/2. the Vco frequency is divided by 32 and counted for tmmt. tmmt is equal to 2vcot_ncyc_rdiv periods of the reference crystal times vcot_xrefdiv_sel Reg0A<11:10> table 21. the frequency result is the value in the vco counter, Vctr, as shown in figure 18. currently only vcot_xrefdiv_sel = 1 is supported. the nominal Vco frequency measured, fvcom, is given by (eQ 1) Where the worst case measurement error, ferro, is: (eQ 2)
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Figure 18. VCO Calibration the period of a single Vco calibration measurement, Tmmt, is given by:
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PLL - fractionaL-n synthesizer - sMt
(eQ 3) Where ncyc vcot
= vcot_ncyc_rdiv Reg0A<5:2> table 21 = ref tune clock division ratio, vcot_xrediv_sel Reg0Ah<11:10>, table 21 note: only vcot = 0 is supported currently
a 5-bit switched resonator Vco, for example, nominally requires 5 measurements for calibration, worst case 6, hence total calibration time, worst case, is given by: (eQ 4) normally we wish the absolute value of ferro to be less than one half of the Vco switched resonator step size specified for the switched resonator Vco.
VCO Auto Tuning Example
suppose our target frequency is to operate at 2.3 Ghz with a nominal 1.5V on the charge pump. our example crystal is 50 Mhz and vcot_xrefdiv_sel divider is 1, hence the auto calibration clock = 50 Mhz. note, when using autocal, the maximum input crystal cannot exceed 60 Mhz. We must decide how long, and how accurate we need to make the tuning. suppose the switched resonator lsb steps are 6.5 Mhz nominal, 6 Mhz worst case. a reasonable calibration target would be to set the calibration frequency error to one half the Vco lsb steps, i.e. ferro <= 3 Mhz. With some reasonable margin, lets target 2 Mhz ferro worst case. Using (eQ 1) we see that the minimum calibration measurement time for a single measurement must be (eQ 5) hence we must choose ncyc such that Tmmt >Tmmtmin solving for (eQ 3) (eQ 6)
We arrive at a value of 10 for ncyc, and hence a single measurement period is Tmmt = 32 usec, the worst case frequency error of the measurement is 2 Mhz and the total time to run the full calibration for a 5 bit switched Vco is six measurements worst case, hence Tcal = 6 Tmmt = 192 usec, plus time for six Vco serial port transfers and state machine housekeeping, typically about 90*R/fxtal, about 1.8 usec more. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Example Calibration Procedure with an Example External VCO
Using the above example calculation for calibration time and accuracy, the procedure to run the calibration is as follows using an example Vco at 2.3 Ghz: the example Vco must first be set up to operate in the desired band, with, in this example, a 50 Mhz crystal and a 50 Mhz PfD frequency. a. setup the Vco register as required by the Vco (Reg0Bh table 22) b. input a reference signal at 50 Mhz c. set the ref divider to divide by 1 , rfp_div_ratio = 00 0000 0000 0001, (Reg03h<13:0> table 14) d. set the integer division, intg = 23d = 002eh (Reg0Fh table 26) then set up the auto calibration features as follows: e. set the auto calibration time by setting vcot_ncyc_rdiv = 1010 (Reg0Ah<5:2> table 21) f. enable the auto calibration feature by setting vcot_auto_start (Reg0Ah<0> table 21) then program the fractional frequency to start the calibration and change frequencies. g. set the fractional register to zero in this example, frac = 000000h (Reg10h table 27) the last step of programming the frequency register initiates the calibration which will run in about 124 usec, as per our calculation. the state machine will write the autotune result into Reg20h table 42. the synthesizer will then be tuned to the commanded output frequency with the optimized switch setting on the Vco. the normal locking time will apply after the calibration is run. the optimum tuning setting for this frequency may be read by the host from read only register vcot_caps Reg20h<7:0> (table 42) and stored for later use for faster tuning to this frequency.
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Manual VCO Control for Fast Frequency Changes
if the auto calibration reading is run first for a given frequency and the calibration settings are read and stored for later use in the host, then a frequency change can be run without re-running the autocal routine. assume that the Vco band and reference are all programmed correctly in advance. further that we disable the auto calibration feature by clearing vcot_auto_start (Reg0Ah<0> table 21). then a frequency change is executed as follows: a. Write the calibration switch setting for the desired frequency to spivco_direct_data (Reg0Bh table 22). (Vco specific) b. if necessary set the integer frequency register dsm_intg (Reg0Fh table 26) c. Write the fractional register to trigger the frequency change frac (Reg10h table 27) d. the synthesizer then automatically updates the fractional divider and initiates the Vco serial Port transfer for the new frequency
Calibration Polarity, Tune Word Inversion & Active Opamp Loop Filters
vcot_invert_outdata (Reg0Ah<6> table 21) inverts the Vco tuning cap polarity. the polarity must be set to match the Vco polarity in question or the autotune search algorithm will not work. this bit is normally set if an active loop filter is used with an inverting opamp with a positive tuning slope Vco vcot_swap_outdata (Reg0Ah<7> table 21) swaps the cap data left to right. this makes it easy to match the Vco in use. Binary weighted caps are expected.
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Temperature Sensor
the hMc702LP6ce features a built in temperature sensor which may be used as a general purpose temperature sensor. the temperature sensor is enabled via tsens_spi_enable (Reg1Eh=1 table 40) and when enabled draws 2 ma. the temperature sensor features a built in 3-bit quantizer that allows the temperature to be read in register tsens_ temperature (Reg21h table 43). the temperature sensor data converter is not clocked. Updates to the temperature sensor register are made by strobing register tsens_spi_strobe (reg00h<3> table 11). the 3-bit quantizer operates over a -40c to +100c range as follows:
tn = floor {(temperature +40) / 17.5 where Tn is the decimal value of register tsens_temperature}
TEMPERATURE SENSOR QUANTIZER OUTPUT 7 6 5 4 3 2 1 0 -40
(eQ 7)
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PLL - fractionaL-n synthesizer - sMt
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 19. Typical Temperature Sensor Quantizer output temperature sensor slope is 17.5 mV/lsb. absolute tolerances on the temperature sensor thresholds may vary by up to 10c worst case. nominal temperature is given by: (eQ 8)
Charge Pump & Phase Frequency Detector (PFD)
the Phase frequency Detector or PfD has two inputs, one from the reference path divider and one from the Vco path divider. the PfD compares the phase of the Vco path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full 2 radians input phase difference.
PFD Functions
phase_sel (Reg05h<0> table 16) inverts the phase detector polarity for use with an inverting opamp or negative slope Vco upout_en in Reg05h<1> table 16 allows masking of the PfD up output, which effectively prevents the charge pump from pumping up. dnout_en in Reg05h<2> table 16 allows masking of the PfD down output, which effectively prevents the charge pump from pumping down.
Charge Pump Tri-State
De-asserting both upout_en and dnout_en effectively tri-states the charge pump while leaving all other functions operating internally.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
PFD Jitter & Lock Detect Background
in normal phase locked operation the divided Vco signal arrives at the phase detector in phase with the divided crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase of the Vco signal and the reference signal vary in time due to the phase noise of the crystal and Vco oscillators, the loop bandwidth used and the presence of fractional modulation or not. the total integrated noise on the Vco path normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. if we wish to detect if the Vco is in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. first, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. the standard deviation of the arrival time of the Vco signal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked Vco has a constant phase noise, 2 (0), at offsets less than the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. the simple locked Vco phase noise approximation is shown on the left of figure 20.
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Figure 20. Synthesizer Phase Noise & Jitter With this simplification the single sideband integrated Vco phase noise, 2 , in rads2 at the phase detector is given by (eQ 9) where 2 ssB(0) is the single sideband phase noise in rads2/hz inside the loop bandwidth, B is the 3 dB corner frequency of the closed loop PLL and n is the division ratio of the prescaler the rms phase jitter of the Vco in rads, , results from the power sum of the two sidebands:
2 = 2 ssB
(eQ 10)
since the simple integral of (eQ 9) is just a product of constants, we can easily do the integral in the log domain. for example if the Vco phase noise inside the loop is -100 dBc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio n=100, then the integrated single sideband phase noise at the phase detector in dB is given by 2dB = 10log (2(0)B n2) = -100 + 50 + 5 - 40 = -85 dBrads, or equivalently = 10 -82/20 = 56 urads rms or 3.2 milli-degrees rms. While the phase noise reduces by a factor of 20logn after division to the reference, the jitter is a constant. the rms jitter from the phase noise is then given by Tjnp = Tref / 2 in this example if the reference was 50 Mhz, Tref = 20 nsec, and hence Tjpn = 178 femto-sec. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
a normal 3 sigma peak-to-peak variation in the arrival time therefore would be 3 2Tjpn = 0.756 ps if the synthesizer was in fractional mode, the fractional modulation of the Vco divider will dominate the jitter. the exact standard deviation of the divided Vco signal will vary based upon the modulator chosen, however a typical modulator will vary by about 3 Vco periods, 4 Vco periods, worst case. if, for example, a nominal Vco at 5 Ghz is divided by 100 to equal the reference at 50 Mhz, then the worst case division ratios will vary by 1004. hence the peak variation in the arrival times caused by modulation of the fractional synthesizer at the reference will be (eQ 11)
PFD Jitter and Lock Detect Background (Continued)
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in this example, tjpk = 200 ps(108-92)/2 = 1600 psec. if we note that the distribution of the delta sigma modulation is approximately gaussian, we could approximate tjpk as a 3 sigma jitter, and hence we could estimate the rms jitter of the modulator as about 1/3 of tjpk or about 532 psec in this example. hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the Vco would be given by the rms sum , where (eQ 12)
in this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation. Bottom line, we have to expect about 1.6 nsec of normal variation in the phase detector arrival times when in fractional mode. in addition, lower Vco frequencies with high reference frequencies will have much larger variations., for example, a 1 Ghz Vco operating at near the minimum nominal divider ratio of 72, would, according to (eQ 11), exhibit about 4 nsec of peak variation at the phase detector, under normal operation. the lock detect circuit must not confuse this modulation as being out of lock.
PFD Lock Detect
lkd_en (Reg01h<11> table 12) enables the lock detect functions of the hMc702LP6ce. the Lock Detect circuit in the hMc702LP6ce places a one shot window around the reference. the one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer. clearing lkd_ringosc_mono_select (Reg1Ah<14> table 36) will result in a nominal 10nsec `analog' window of fixed length, as shown in figure 21. setting lkd_ringosc_mono_select will result in a variable length 'digital' widow. the digital one shot window is controlled by lkd_ringosc_cfg (Reg1Ah<16:15>). the resulting lock detect window period is then generated by the number of ring oscillator periods defined in lkd_monost_duration Reg1Ah<18:17> (table 36). the lock detect ring oscillator may be observed on the GPo2 port by setting ringosc_testmode (Reg1Ah<19> table 36) and configuring the gpo_sel<3:0> = 0111 in (Reg1Bh table 37). Lock detect does not function when this test mode is enabled. lkd_wincnt_max (Reg1Ah<9:0> table 36) defines the number of consecutive counts of the Vco that must land inside the lock detect window to declare lock. if for example we set lkd_wincnt_max = 1000 , then the Vco arrival would have to occur inside the selected lock widow 1000 times in a row to be declared locked. When locked the Lock Detect flag ro_lock_detect (Reg1Fh<0> table 41) will be set. a single occurrence outside of the window will result in clearing the Lock Detect flag, ro_lock_detect.
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For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
the Lock Detect flag ro_lock_detect (Reg1Fh<0> table 41) is a read only register, readable from the serial port. the Lock Detect flag is also output to the LD_SDO pin according to lkd_to_sdo_always (Reg1Ah<13>) and lkd_to_sdo_ automux_en (Reg1Ah<12>), both in table 36. setting lkd_to_sdo_always will always display the Lock Detect flag on LD_DSO. clearing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display the Lock Detect flag on LD_SDO except when a serial port read is requested, in which case the pin reverts temporarily to the serial Data out pin, and returns to the lock detect function after the read is completed.
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Figure 21. Normal Lock Detect Window
Lock Detect with Phase Offset
When operating in fractional mode the linearity of the charge pump and phase detector are more critical than in integer mode. the phase detector linearity is worse when operated with zero phase offset. hence in fractional mode it is necessary to offset the phase of the reference and the Vco at the phase detector. in such a case, for example with an offset delay, as shown in figure 22, the mean phase of the Vco will always occur after the reference. the lock detect circuit window can be made more selective with a fixed offset delay by setting win_asym_enable and win_asym_up_select (Reg1Ah<11> table 36). similarly the offset can be in advance of the reference by clearing win_asym_up_select while leaving win_asym_enable Reg1Ah<10> set both in table 36.
Figure 22. Delayed Lock Detect Window
Cycle Slip Prevention (CSP)
When changing frequencies the Vco is not yet locked to the reference and the phase difference at the PfD varies rapidly over a range much greater than 2 radians. since the gain of the PfD varies linearly with phase up to 2, the gain of conventional PfDs will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. this phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in figure 23. cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal Laplace analysis. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Cycle Slip Prevention (CSP) (Continued)
the hMc702LP6ce PfD features cycle slip Prevention (csP), an ability to virtually eliminate cycle slipping during acquisition. When enabled, the csP feature essentially holds the PfD gain at maximum until such time as the frequency difference is near zero. csP allows significantly faster lock times as shown in figure 23. the use of the csP feature is enabled with pfds_rstb (Reg01<15> table 12). the csP feature may be optimized for a given set of PLL dynamics by adjusting the PfD sensitivity to cycle slipping. this is achieved by adjusting pfds_sat_deltaN (Reg1C<3:0> table 38).
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PLL - fractionaL-n synthesizer - sMt
Figure 23. Cycle Slip Prevention (CSP)
Charge Pump Gain
a simplified diagram of the charge pump is shown in figure 24. charge pump up and down gains are set by cp_ UPcurrent_sel and cp_DNcurrent_sel respectively (Reg07 table 18). normally the registers are set to the same value. each of the UP and Dn charge pumps consist of 5-bit charge pumps with lsb of 125 a. the current gain of the pump, in amps/radian, is equal to the gain setting of this register divided by 2. for example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to '01000' the output current of each pump will be 1ma and the gain Kp = 1ma/2 radians, or 159 ua/rad.
Charge Pump Gain Trim
in most applications Gain trim is not used. however it is available for special applications. each of the UP and Dn pumps may be trimmed separately to more precise values to improve current source matching of the UP and Dn values, or to allow finer control of pump gain. the pump trim controls are 3-bits, binary weighted for UP and Dn, in cp_UPtrim_sel and cp_DNtrim_sel respectively (reg 08h table 19). LsB weight is 14.7 ua, x000 = 0 trim, x001 = 14.7 ua added trim, x111 = 100ua.
Charge Pump Phase Offset
either of the UP or Dn charge pumps may have a Dc leakage or "offset" added. the leakage forces the phase detector to operate with a phase offset between the reference and the divided Vco inputs. it is recommended to operate with a phase offset when using fractional mode to reduce non-linear effects from the UP and Dn pump mismatch. Phase noise in fractional mode is strongly affected by charge pump offset. Dc leakage or "offset" may be added to the UP or Dn pumps using cp_UPoffset_sel and cp_DNoffset_sel (Reg08 table 19). these are 4 bit registers with 28.7ua LsB. Maximum offset is 430ua. as an example, if the main pump gain was set at 1ma, an offset of 373ua would represent a phase offset of about (392/1000)*360 = 133degrees.
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
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Figure 24. Charge Pump Gain, Trim and Phase Offset Control
Frequency Programming
the hMc702LP6ce can operate in either fractional mode or integer mode. in integer mode of operation the delta sigma modulator is disabled. frequency programming and mode control is described below.
Fractional Frequency
the fractional frequency synthesizer, when operating in fractional mode, can lock to frequencies which are fractional multiples of the reference frequency. fractional mode is the default mode. to run in fractional mode ensure that dsm_integer_mode reg12h<3> table 29 is clear and dsm_rstb is set reg01<13> table 12. then program the frequency as explained below: the output frequency of the synthesizer is given by, fvco, where
Fractional Frequency of VCO
(eQ 13)
where Nint Nfrac R fxtal as an example: fxtal R fref Nint Nfrac = 50 Mhz =1 = 50 Mhz = 92 =1 is the integer division ratio, an integer number between 36 and 65,533 (dsm_intg (Reg0Fh table 26)) is the fractional part, a number from 1 to 224 (dsm_frac Reg10h table 27) is the reference path division ratio, (rfp_div_ratio Reg03h<13:0> table 14) is the frequency of the crystal oscillator input (Xsin or Xref figure 10)
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PLL - fractionaL-n synthesizer - sMt
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
(eQ 14)
in this example the output frequency of 9,600,000,005.96 hz is achieved by programming the 16-bit binary value of 92d = 5c = 0000 0000 0101 1100 into dsm_intg. similarly the 24-bit binary value of the fractional word is written into dsm_frac, 1d = 000 001h = 0000 0000 0000 0000 0000 0001 Example 2: set the output to 12.600 025 Ghz using a 100 Mhz reference, r=2. find the nearest integer value, nint, nint = 126, fint = 12.600 000 Ghz this leaves the fractional part to be ffrac =25 khz (eQ 15)
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PLL - fractionaL-n synthesizer - sMt
since Nfrac must be an integer number, the actual fractional frequency will be 24,998.19 hz, an error of 1.81 hz. here we program the 16-bit nint = 126d = 7eh = 0000 0000 0111 1110 and the 24-bit nfrac = 4194d = 1062h = 0000 0100 0001 0010 in addition to the above frequency programming words, the fractional mode must be enabled using the frac register. other DsM configuration registers should be set to the recommended values. register setup files are available on request.
Integer Frequency
the synthesizer is capable of operating in integer mode. in integer mode the digital modulator is normally shut off and the division ratio of the Vco divider is set at a fixed value. to run in integer mode set dsm_integer_mode (Reg12h<3> table 29) and clear dsm_rstb (Reg01h<13> table 12). then program the integer portion of the frequency, NINT, as explained by (eQ 13), ignoring the fractional part.
Frequency Hopping Trigger
if the synthesizer is in fractional mode, a write to the fractional frequency register, Reg10h table 27, will initiate the frequency hop on the falling edge of the 31st clock edge of the serial port write (see figure 29). if the integer frequency register, Reg0Fh table 26, is written when in fractional mode the information will be buffered and only executed when the fractional frequency register is written. if the synthesizer is in integer mode, a write to the integer frequency register, Reg0Fh table 26, will initiate the frequency hop on the falling edge of the 31st clock edge of the serial port write (see figure 29).
Power On Reset (POR)
normally all logic cells in the hMc702LP6ce are reset when the device digital power supply, DVDD, is applied. this is referred to as Power on reset, or just Por. Por normally takes about 500us after the DVDD supply exceeds 1.5V, guaranteed to be reset in 1msec. once the DVDD supply exceeds 1.5V, the Por will not reset the digital again unless the supply drops below 100mV.
11 - 28
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Soft Reset
the sPi registers may also be soft reset by an sPi write to strobe global_swrst_regs (Reg00h<0> table 11). all other digital, including the fractional modulator, may be reset with an sPi write to strobe global_swrst_dig (Reg00h<1> table 11).
Hardware Reset
the sPi registers may also be hardware reset by holding rstB, pin 19, low.
Power Down
the hMc702LP6ce may be powered down by writing a zero to Reg01h table 12. in power down state the hMc702LP6ce should draw less than 10ua. it should be noted that Reg01h is the enable and reset register which controls 16 separate functions in the chip. Depending upon the desired mode of operation of the chip, not all of the functions may be enabled when in operation. hence power up of the chip requires a selective write to Reg01 bits. an easy way to return the chip to its prior state after a power down is to first read Reg01h and save the state, then write a zero to Reg01h for reset and then simply rewrite the previous value to restore the chip to the desired operating mode.
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PLL - fractionaL-n synthesizer - sMt
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CW Sweeper Mode
the hMc702LP6ce features a built in frequency sweeper function. this function supports external or automatic triggered sweeps. the maximum sweep range is limited to 510 x fxtal/r. for example, with a 10 Mhz comparison frequency, the maximum sweep range is 5100 Mhz. the start and end frequency points must be within 5100 Mhz of one another sweeper Modes include: a. 2-Way sweep Mode: alternating positive and negative frequency ramps. b. 1-Way sweep Mode c. single step ramp Mode applications include test instrumentation, fMcW sensors, automotive radars and others. the parameters of the sweep function are illustrated in figure 26. the sweep generator is enabled with ramp_enable in (Reg14h<1> table 30). the sweep function cycles through a series of discrete frequency values, which may be a. stepped by an automatic sequencer, or b. single stepped by individual triggers in single step Mode. triggering of each sweep, or step, may be configured to operate: a. Via a serial port write to Reg14h<2> ramp_trigg (if reg 14h<2> = 0 ) b. automatically generated internally, c. triggered via ttL input on GPo3 reg14h<5> = 1. sweep parameters are set as follows: initial frequency, fo = current frequency value of the synthesizer, (eQ 15) final frequency, ff = frequency of the synthesizer at the end of the ramp the frequency step size while ramping is controlled by rampstep, (Reg15h table 31). frequency step size step = rampstep * fxtal / 223 * R where r is the value of the reference divider (rfp_div_ratio in table 14) For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
CW Sweeper Mode (Continued)
clearing or setting ramp_startdir_dn, (Reg14h<4> table 30), sets the initial ramp direction to be increasing or decreasing in frequency respectively. setting ramp_singledir (Reg14h<7> table 30), restricts the direction of the sweep to the initial sweep direction only. the sweeper timebase Tref is the period of the divided reference, fPFD, at the phase detector Tref the total number of ramp steps taken in a single sweep is given by ramp_steps_number in reg16h table 32. the total time to ramp from fo to ff is given by Tramp = Tref the final ramp frequency, ff, is given by = i + step
* *
ramp_steps_number
ramp_steps_number
sweeper action at the end of sweep depends upon the mode of the sweep: a. With both ramp_singledir and ramp_repeat_en disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the final frequency ff, until a new trigger is received. the next trigger will reverse the current sequence, starting from ff, and stepping back to fo. odd triggers will ramp in the same direction as the initial ramp, even triggers will ramp in the opposite direction. b. with ramp_singledir enabled and ramp_repeat_en disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the final frequency ff, until a new trigger is received. the second trigger will hop the synthesizer back to the initial frequency, fo. the third trigger will restart the sweep from fo. hence all odd numbered triggers will start a new ramp in the same direction as the initial ramp, even numbered triggers will hop the synthesizer from the current frequency to fo , where it will wait for a trigger to start a sweep.
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PLL - fractionaL-n synthesizer - sMt
Ramp Busy
in all types of sweeps ramp_busy will indicate an active sweep and will stay high between the 1st and nth ramp step. ramp_busy may be monitored one of two ways. ramp_busy is readable via read only register Reg1Fh<5> table 41. ramp_busy may also be monitored on GPo2, hardware pin 24, by setting Reg1Bh<3:0> =8h table 37.
Autosweep Mode
the autosweep mode is similar to figure 26 except that once started, triggers are not required. once enabled, (ramp_ repeat_en=1 Reg14h<3> table 30) the autosweep mode initiates the first trigger, steps n times, one step per ref clock cycle, and then waits for the programmed dwell period and automatically triggers the ramp in the opposite direction. the sweep process continues alternating sweep directions until disabled. dwell_time (Reg17h table 33) controls the number of Tref periods to wait at the end of the ramp before automatically retriggering a new sweep.
2-Way Sweeps
if ramp_repeat_en (Reg14h<3> table 30) is cleared, then the ramps are triggered by a. Writing to ramp_trigg (Reg14h<2> table 30), if bit <2> = 0, or b. by rising edge ttL signal input on GPo3, if ramp_trig_ext_en is set, and GPo3 is enabled. all functions are the same in figure 26 for autosweep or 2-Way triggered sweeps, the only difference is the trigger source is generated internally for autosweep, and is input via serial port or GPo3 for triggered sweeps. Sweep_busy will go high at the start of every ramp and stay high until the nth step in the ramp.
11 - 30
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
11
Figure 26. 2-Way Sweep Control via Trigger
Triggered 1-Way Sweeps
1-Way sweeps are shown in figure 27. Unlike 2-Way sweeps, 1-Way sweeps require that the Vco hop back to the start frequency after the dwell period. triggered 1-Way sweeps also require a 3rd trigger to start the new sweep. the 3 rd trigger must be timed appropriately to allow the Vco to settle after the large frequency hop back to the start frequency. subsequent odd numbered triggers will start the 1-Way sweep and repeat the process.
Figure 27. 1-Way Sweep Control
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PLL - fractionaL-n synthesizer - sMt
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Single Step Ramp Mode
a single step 1-Way ramp is shown in figure 28. in this mode, a trigger is required for each step of the ramp. single step will function in either 1-Way or 2-Way ramps. similar to autosweep, the ramp_busy flag will go high on the first trigger, and will stay high until the nth trigger. the n+1 trigger will cause the ramp to jump to the start frequency in 1-way ramp mode. the n+2 trigger will restart the 1-way ramp.
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PLL - fractionaL-n synthesizer - sMt
Figure 28. Single Step Ramp Mode
the user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. if the loop bandwidth in use is much wider than the rate of the steps then the locking will be very fast and the ramp will have a staircase shape. if the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not fully settle before a new frequency step is received. hence the swept output will have a small lag and will sweep in a near continuous fashion.
MAIN SERIAL PORT
the hMc702LP6ce features a four wire serial port for simple communication with the host controller. register types may be read only, Write only, read/Write or strobe, as described in the registers descriptions. the synthesizer also features an auxiliary 3-wire serial port, known as the Vco serial Port. the Vco serial Port is a write only interface from the synthesizer to an optional switched resonator Vco that supports 3-wire serial port control. typical main serial port operation can be run with scLK at speeds up to 50 Mhz. serial port registers are described in the section reGister MaP.
[1] Phase-error Measurement and compensation in PLL frequency synthesizers for fMcW, sensors--i: context and application, Pichler, stelzer, Member, ieee, seisenberger, and Vossiek, ieee transactions on circuits and systems--i, VoL. 54, no. 5, May 2007
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Serial Port WRITE Operation
aVDD = DVDD = 3V 10%, aGnD = DGnD = 0V
Table 4. Timing Characteristics
Parameter t1 t2 t3 t4 t5 t6 t7 Conditions sen to scLK setup time sDi to scLK setup time sDi to cLK hold time scLK high duration scLK low duration sen high duration sen low duration Min. 8 10 10 8 8 640 20 Typ. Max Units nsec nsec nsec nsec nsec nsec nsec
a typical Write cycle is shown in figure 29. a. the Master (host) both asserts sen (serial Port enable) and clears sDi to indicate a Write cycle, followed by a rising edge of scLK. b. the slave (synthesizer) reads sDi on the 1st rising edge of scLK after sen. sDi low initiates the Write cycle (/Wr) c. host places the six address bits on the next six falling edges of scLK, MsB first. d. slave registers the address bits in the next six rising edges of scLK (2-7). e. host places the 24 data bits on the next 24 falling edges of scK, MsB first . f. slave registers the data bits on the next 24 rising edges of scK (8-31). g. sen is de-asserted on the 32nd falling edge of scLK. h. the 32nd rising edge of scLK completes the cycle
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PLL - fractionaL-n synthesizer - sMt
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Figure 29. Serial Port Timing Diagram - WRITE
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Main Serial Port READ Operation
the synthesizer uses the multi-purpose pin, LD_SDO, for both Lock Detect and serial Data out (sDo) functions. the registers lkd_to_sdo_automux_en (Reg1A<12>) and lkd_to_sdo_always (Reg1A<13> table 36) determine how the Data output pin is muxed with the Lock Detect function. if both of the registers are cleared, then the pin is exclusively sDo. if automux is enabled, the pin switches to sDo when the rD function is sensed on the 1st rising edge of scLK. if lkd_to_sdo_always is set, then the pin LD_SDO is dedicated for Lock Detect only, and it is not possible to read from the synthesizer. a typical reaD cycle is shown in figure 30. a. the Master (host) asserts both sen (serial Port enable) and sDi to indicate a reaD cycle, followed by a rising edge scLK b. the slave (synthesizer) reads sDi on the 1st rising edge of scLK after sen. sDi high initiates the reaD cycle (rD)
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PLL - fractionaL-n synthesizer - sMt
c. host places the six address bits on the next six falling edges of scLK, MsB first. d. slave registers the address bits on the next six rising edges of scLK (2-7). e. slave places the 24 data bits on the next 24 rising edges of scK (8-31), MsB first . f. host registers the data bits on the next 24 falling edges of scK (8-31). g. sen is de-asserted on the 32nd falling edge of scLK. h. the 32nd falling edge of scLK completes the cycle
Figure 30. Serial Port Timing Diagram - READ
VCO SERIAL PORT
the Vco serial Port is a 3-wire serial port that may be used to control external step tuned Vcos that support serial port control. Visit the hittite website or contact hittite sales for a full list of compatible Vcos. the Vco serial Port is a 3-wire serial port that may be used to control external step tuned Vcos that support serial port control. the 3-wire Vco serial port uses the following pins, as shown in figure 31: VsDo: Vco serial Port Data out VscK: Vco serial Port clock VsLe: Vco serial Port Latch enable the Vco serial Port transfers the contents of the 16-bit register spivco_direct_data (Reg0Bh table 22) to the Vco upon receipt of a frequency change command. the lsbs of spivco_direct_data are the switch settings for the Vco and may be set directly or by the autotune routine described in the section step tuned Vco support. Multiple Vco formats are supported for autotuning. Vco tuning bits are configured with sar_bits_number (Reg0Dh<5:4> table 24). Multiple Vco sPi formats are also supported and are configured by spivco_mode (Reg0Dh<1:0> table 24).
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
the msbs of Reg0Bh, are Vco control bits and are also Vco specific. the Vco should be designed to only register the data upon receipt of the latch signal, VsLe. Multiple Vco control can be implemented by addressing the individual Vcos.
VCO Serial Port WRITE Operation
DVDD = 3V 10%, DGnD = 0V
Table 5. Timing Characteristics
Parameter t1 t2 t3 t4 t5 t6 Conditions VsLe to VsDo setup time VsDo to VscK setup time VsDo to VscK hold time VscK high duration VscK low duration VsLe high duration Min. 8 10 10 8 8 8 Typ. Max Units nsec nsec nsec nsec nsec nsec
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PLL - fractionaL-n synthesizer - sMt
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Vco serial port status is flagged in read only register spi_vco_busy (Reg1Fh<4> table 41). individual step tuned Vcos may have different capabilities, such as power down, or divide by two outputs, and may also have different number of switches in the resonator. the hMc702LP6ce can adapt its control format and number of tuning bits used in the autotuning routine as described in Reg0Dh table 24.
16-Bit VCO Write Cycle
hMc Vcos that support the 16-bit write cycle described here are fully addressable via the VsPi control. a typical 16-bit Vco Write cycle is shown in figure 31. a. the synthesizer (Master) both clears VsLe (Vco serial Port Latch) and places data bit d8 (msb) on VsDo. b. the synthesizer places a rising edge on VscK to shift d8 into the Vco c. synthesizer places the next eight data bits, d7:d0, on the next eight falling edges of VscLK, LsB last. d. the synthesizer clocks each data bit on the next eight rising edges of VscLK . e. synthesizer places the next four Vco register bits, r3:r0, on the next four falling edges of VscLK, LsB last. f. synthesizer places the next three Vco address bits, a2:a0, on the next three falling edges of VscLK, LsB last. g. the synthesizer asserts VsLe after the falling edge of the 16th VscK, which latches the data into the Vco h. the synthesizer clears VsLe to complete the cycle
Figure 31. VCO Serial Port Timing Diagram - WRITE ONLY For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Typical Step Tuned VCO Register Map Step Tuned VCO Registers Example
note: hMc step tuned Vcos come in different configurations. the following four registers give examples of typical control registers in hMc step tuned Vcos. consult the Vco data sheet to confirm available Vco features.
Table 6. VSPI Format
Bit [2:0] [6:3] [15:7] Vco iD Vco register address Vco Data Name Width 3 4 9 Default n/a n/a n/a Description Vco address, MsB first Vco register address Vco Data Bits
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PLL - fractionaL-n synthesizer - sMt
Table 7. VCO R00 (Switch Controller Register)
Bit [0] Name enable calibration Width 1 Default 0 Description reserved for calibration mode, forces a locally generated temperature compensated voltage on the Vco tuning port 6 bit tuning control 000000 minimum tuning capacitance 000001 next to minimum ... 111111 maximum tuning capacitance not Used
[6:1]
tune control
6
100000 b
[8:7]
not Used
2
Table 8. VCO R01 (Enable Register)
Bit [3:0] [4] [5] [6] [7] [8] reserved PLL Buffer en Divider en Buffer en Vco en Global en 1 1 Name Width 4 1 1 1 1 Default x 1 1 1 1 reserved PLL Buffer enable (Low power output to PLL) Divider enable (if present) Buffer enable (high power rf output to application) Vco enable Global enable 0: forces all cells to power down state 1: enables individual cell state control via bits 4 thru 7. Description
Table 9. VCO R02 (Bias Control Register)
Bit Name PLL Buffer Bias Bits (MsB:LsB) Width Default 0: Min Bias 1: next to min bias 2: next to max bias 3: Max Bias 0: Min Bias 1: next to min bias 2: next to max bias 3: Max Bias 0: Min Bias 1: next to min bias 2: next to max bias 3: Max Bias Description
[1:0]
2
1
[3:2]
Divider or Doubler Bias Bits (MsB:LsB), if present in Vco
2
00
[5:4]
Mixer Buffer Bias Bits (MsB:LsB) reserved
2
00
[8:6]
3
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 10. VCO R03 (Temperature & Gain Control Register)
Bit [4:0] reserved temp compensation offset control (MsB: LsB) Name 5 Default x reserved 0: reduce tuning voltage 50mV 1: Use default tuning voltage 2: increase tuning voltage 50mV 3: increase tuning voltage 100mV 0: Min Gain 1: next to Min Gain 2: next to Max Gain 3: Max Gain Description
[6:5]
2
1
[8:7]
PLL Buffer Gain control (MsB: LsB)
2
1
REGISTER MAP Reg 00h Chip ID (Read Only) Register
Bit [23:0] Type ro chip iD Name Width 24 Default 581504 chip iD Description
11
Default 0 0 0 0 Description strobe to soft reset the sPi registers strobe to soft reset the rest of digital reserved strobe to clock the temp measurement on demand
Table 11. Reg 00h Strobe (Write Only) Register
Bit 0 1 2 3 Type str str str str Name global_swrst_regs global_swrst_dig mcnt_resynch tsens_spi_strobe Width 1 1 1 1
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PLL - fractionaL-n synthesizer - sMt
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 12. Reg 01h Enable & Reset Register
Bit 0 1 2 Type r/W r/W r/W Name malg_vcobug_en mag_bias_en rfp_div_en 1 1 1 Default 1 1 0 Bias enable enables / holds refdiv in reset holding ref divider in reset is equivalent to bypassing the divider, see figure 10 enables clock gate for xtal muxed (sq or sin) reference to digital enables divided reference clock to the digital see figure 10 enables square wave xtal clock to main digital see figure 10 enables sine wave xtal clock to main digital see figure 10 enables square wave ref Buffer, see figure 10 enables sine wave ref Buffer, see figure 10 1= divided Vco as digital, modulator clock 0= Divided ref path as the enables the prescaler bias enable / resetb to digital lockdetect circuit and PfD's lockdetect output gates charge Pump enable, disable is tri-stated output 1 - enables fractional modulator see also dsm_integer_mode Reg12h<3> 1 - enables lock detect circuit csP PfD ff rstb 1 - enables the cycle slip Prevention (csP) feature of the PfD Description Vco Buffer enable
3 4 5
r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W
xrefmux_todig_en rfp_div_todig_en rfp_sqr_todig_en rfp_sin_todig_en rfp_bug_sq_en rfp_bug_sin_en vcop_todig_en vcop_presc_en pfd_lkd_en cp_en dsm_rstb lkd_rstb pfds_rstb
1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 1 0 0 1 0 1 0 0 1
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PLL - fractionaL-n synthesizer - sMt
6 7 8 9 10 11 12 13 14 15
Table 13. Reg 02h Serial Data Out Force Register
Bit 0 Type r/W Name malg_sdo_driver_force_val Default 1 Description serial Data out force value this value may be forced onto LD_sDo by setting malg_sdo_driver_force_en serial Data out en force enable Places value from malg_sdo_driver_force_val on sDo
1
r/W
malg_sdo_driver_force_en
1
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 14. Reg 03h Reference Path Register
Bit Type Name Default Description Divides the crystal input by this number `r' if rfp_div_en=1 and rfp_div_select = 1 rfp_div_ratio = 0 not allowed 2<=div_ratio<=2^14 see figure 10 1 = reference divider enabled 0 = bypass ref divider see figure 10 1 = auto ref divider enable or bypass is automatic if rfp_div_ratio = 1, bypass divider if rfp_div_bypass ~=1 use divider see figure 10 selects sine wave reference for normal operation see figure 10
13:0
r/W
rfp_div_ratio also referred to as `r'
0
14
r/W
rfp_div_select
0
15
r/W
rfp_auto_refdiv_sel_en
0
16
r/W
rfp_buf_sin_sel
0
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PLL - fractionaL-n synthesizer - sMt
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Table 15. Reg 04h Prescaler Duty Cycle Register
Bit 0 Type r/W Name vcop_dutycycmode Default 0 Description extends the low time from 30 to 94 Vco cycles for large divide ratios
Table 16. Reg 05h Phase Freq Detector Register (pfd)
Bit Type Name Default Description inverts PfD Polarity 0 = Passive filter +ve slope Vco 1 = Passive filter -ve slope Vco 1 = active inverting filter, +ve slope Vco 0 = active inverting filter, -ve slope Vco allows masking of the up outputs between PfD and cP allows masking of the dn outputs between PfD and cP
0
r/W
pfd_phase_sel
0
1 2
r/W r/W
pfd_upout_en pfd_dnout_en
1 1
Table 17. Reg 06h Phase Freq Detector Delay Register
Bit 2:0 Type r/W pfd_del_sel Name Default 2 Description Delay line setpoint to PfD
Table 18. Reg 07h Charge Pump UP/DN Control Register
Bit 4:0 9:5 Type r/W r/W Name cp_UPcurrent_sel cp_Dncurrent_sel Default 16 16 Description sets charge-Pump Up gain, 125ua lsb, binary, 4ma max sets charge-Pump Dn gain, 125ua lsb, binary, 4ma max
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HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 19. Reg 08h Charge Pump Trim & Offset Register
Bit 3:0 7:4 11:8 15:12 17:16 Type r/W r/W r/W r/W r/W cp_UPtrim_sel cp_Dntrim_sel cp_UPoffset_sel cp_Dnoffset_sel cp_amp_bias_sel Name Default 0 0 4 0 2 Description trim Up gain, 14.3ua lsb, binary, 100ua max trim Dn gain, 14.3ua lsb, binary, 100ua max Up offset leakage current, 28.7ua lsb, binary, 430ua max Dn offset leakage current, 28.7ua , binary, 430uamax charge Pump Dummy Branch op amp bias selection, 100ua
Table 20. Reg 09h Charge Pump EN Register
11
PLL - fractionaL-n synthesizer - sMt
Bit 0 1
Type r/W r/W
Name cp_pull_updn_en cp_pull_dn_upb
Default 0 0
Description enables cP UP/Down control reg09 [1] 0 - forces charge Pump Up when reg09[0]=1 1 - forces charge Pump Dn when reg09[0]=1
Table 21. Reg 0Ah VCO Auto Tune & Control Register
Bit 0 1 Type r/W r/W vcot_auto_start vcot_man_start Name Default 0 0 Description enables auto start of Vco cap tuning when frac word is written to spi starts manual vco tuning when auto_start=0 (must be cleared to 0 before another tune) exponent selection for number of rdiv cycles to wait during measurement (effects time to perform the measurement and hence the accuracy) inverts the vco tuning cap polarity swaps the cap tuning data (left-to-right) force enable for the Vco tuning cap word obsolete enables double buffer for vco caps. caps will go to the vco when dsm_frac reg is written xref divider generate vco tuning calibration clock, and Vco serial Port clock VscK from the crystal input (see figure 10) . this divider affects calibration time and accuracy, currently only divby1 is supported 00-->div by 1 01-->div by 2 not supported 10-->div by 4 not supported 11-->div by 8 not supported
5:2 6 7 8 9
r/W r/W r/W r/W r/W
vcot_ncyc_rdiv vcot_invert_outdata vcot_swap_outdata vcot_force_data_en vcot_force_dblbuff_mode
2 0 0 0 0
11:10
r/W
vcot_xrefdiv_sel
0
Table 22. Reg 0Bh VCO Tuning & Control Register
Bit 15:0 Type r/W Name spivco_direct_data Default 0 Description Used to set Vco control settings Vco specific, see Vco seriaL Port description
11 - 40
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 23. Reg 0Ch VCO Auto Tune Wait Register
Bit 13:0 Type r/W vcot_initial_wait Name Default 256 Description initial wait time (xtal cycles) after tri-stating charge-pump to start Vco tuning
Table 24. Reg 0Dh VCO Control Register
Bit Type Name Default Description support for different Vco sPi formats 0: 16-bit VsPi 1: 10-bit VsPi with 5-bit sar 2: 10-bit VsPi with 6-bit sar 3: blank VcosPi data csP speedup function increases csP current when Lock Detect window exceeds threshold 0: disabled 1: 1nsec threshold 2: 3nsec threshold 3: 5nsec threshold autotune successive approximation register (sar) autotune algorithm supports Vcos with 5, 6, 7 or 8-bit step tuning 8-n = sar bits 0: 8 bit sar 1: 7 bit sar 2: 6 bit sar 3: 5 bit sar 0 : disabled 1: automatically runs the autotuning routine to relock the Vco if loss of lock is detected
1:0
r/W
spivco_mode
0
3:2
r/W
f1_modesel
0
11
PLL - fractionaL-n synthesizer - sMt
11 - 41
5:4
r/W
sar_bits_number
0
6
r/W
autocal_when_unlocked
0
Table 25. Reg 0Eh Reserved
Bit 23:0 Type r/W reserved Name Default 0 reserved Description
Table 26. Reg 0Fh Integer Division Register
Bit 15:0 Type r/W dsm_intg Name Default 200d Description unsigned integer portion of Vco divider value, also known as NINT, see (eQ 12)
Table 27. Reg 10h Fractional Division Register
Bit 23:0 Type r/W dsm_frac Name Default 0 Description unsigned fractional portion of Vco divider also known as NFRAC, see (eQ 12)
Table 28. Reg 11h Seed Register
Bit 23:0 Type r/W dsm_seed Name Default 0 Description unsigned seed value for modulator sets the start phase of the modulator
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 29. Reg 12h Delta Sigma Modulator Register
Bit 0 1 2 Type r/W r/W r/W Name dsm_ref_clk_select dsm_invert_clk_sd3 dsm_invert_clk_rph Default 0 1 0 invert clk inverts the ref clock phase 1- enables integer Mode, bypasses the modulator, leaves it running see also dsm_rstb reg01h<13> to disable the modulator Description use reference instead of divider
3
r/W
dsm_integer_mode
0
4 5
r/W r/W r/W r/W r/W r/W r/W
reserved reserved dsm_xref_sin_select dsm_autoseed dsm_order dsm_quant_max dsm_quant_min
0 0 0 1 2 4'b0111 4'b1000 when xref is selected specifies that the sine source is used automatic seed load when changing the frac part, uses value in seed 00-first order 01-second 10-third fb 11-third ff max value allowed out of modulator quantizer limits are +7 to -8, typ 3 or 4 min value allowed out of modulator quantizer limits are +7 to -8, typ 3 or 4
11
PLL - fractionaL-n synthesizer - sMt
6 7 9:8 13:10 17:14
Table 30. Reg 14h CW Sweep Control Register
the maximum sweep range is limited to 510 x fxtal/r
Bit 0 1 Type r/W r/W clear_ovf_undf ramp_enable Name Default 0 0 Description asynchronous clear for ovf/undf flags ramp en/rstb 1= enables the cW ramp function Write always triggers ramps if bit <2> = 0, if bit <2> = 1, ramp will not trigger, bit <2> must be reset to 0 first ramp repeat seq enable 1= enables autotrigger of ramps 0 = ramp_trigg starts each ramp ramp start direction 1= start with ramp Down 0= start with ramp Up enable hardware trigger on GPo3 pin ramp single step, advances the ramp to the next step, and holds frequency ramps in one direction only with hop to start at end of ramp
2
r/W
ramp_trigg
0
3
r/W
ramp_repeat_en
0
4 5 6 7
r/W r/W r/W r/W
ramp_startdir_dn ramp_trig_ext_en ramp_singlestep ramp_singledir
0 0 0 0
Table 31. Reg 15h CW Sweep Ramp Step Register
the maximum sweep range is limited to 510 x fxtal/r
Bit 23:0 Type r/W ramp_step Name Default 2048 ramp step size Description
11 - 42
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 32. Reg 16h CW Sweep Ramp Step Number Register
the maximum sweep range is limited to 510 x fxtal/r
Bit 23:0 Type r/W Name ramp_steps_number Default 2048 Description ramp number of steps in ramp
Table 33. Reg 17h CW Sweep Dwell Time Register
Bit 23:0 Type r/W Name ramp_dwell_time Default 2048 Description ramp number of cycles to hold at top/bottom in repeat mode
Table 34. Reg 18h Auxiliary Oscillator Register 1
Bit Type Name Default Description selects the input clk for auxclk 0:vcodiv 1:xrefsq or sin 2:refdiv 3:ring oscillator from mono, est 300 Mhz to 1 Ghz 0: bypass-no delay 1: pass through w/ delay 2: ring-out constant 3: ring-out seeded/gated divider selection auxclk value divby 000 001 010 011 100 101 110 111 1 2 4 6 8 10 12 14
11
PLL - fractionaL-n synthesizer - sMt
11 - 43
1:0
r/W
dsmclk_auxclk_insel
0
3:2
r/W
dsmclk_auxclk_modesel
0
6:4
r/W
dsmclk_auxclk_divsel
2
7 8 9
r/W r/W r/W
dsmclk_auxclk_sel dsmclk_auxmod_lfsr_en dsmclk_auxmod_accum_en
0 0 0
selects auxclk (if=1) as natural reference clk input of sigma delta enables 10-bit lfsr inside the delay modulator (clocked by auxclk or auxclkb) enables 8-bit accumulator inside the delay modulator (clocked by auxclk or auxclkb) delay modulation mode 0: auxmod_lodly_in passthrough 1: accumulator based square-wave 2: lfsr (lo-amp) 3: lfsr (hi-amp) step-size of accumulator (changes square-wave value once it wraps through 256) value of delay-element (when auxmod_mode=0) or low value used during sq-wave modulation
11:10
r/W
dsmclk_auxmod_mode
0
19:12 22:20
r/W r/W
dsmclk_auxmod_fracstep dsmclk_auxmod_lodly
3 0
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 35. Reg 19h Auxiliary Oscillator Register 2
Bit 2:0 3 4 Type r/W r/W r/W Name dsmclk_auxmod_hidly dsmclk_auxmod_clkinv dsmclk_auxmod_clkwring Default 7 1 9 Description hi value of delay element during sq-wave modulation optionally inverts auxclk as used by the modulator select LKD ringosc to clock the Lfsr
Table 36. Reg 1Ah Lock Detect Register
Bit 9:0 Type r/W r/W r/W r/W lkd_wincnt_max lkd_win_asym_enable lkd_win_asym_up_select lkd_to_sdo_automux_en Name Default 10'd40 0 0 0 Description threshold count in the timer window to declare lock (reference cycles) enables asymmetric lock detect window (nominal 10nsec) sets polarity of the window Muxes the lkd output signal to sDo when sDo is not being used for Main serial Port Data outputs (read operation) Muxes the lkd output signal to sDo always, not possible to do Main serial Port read in this state 1 select ringosc based oneshot for lock detect window 0 selects analog based oneshot "00" fastest "11" slowest "00" shortest "11" longest enables the ring osc by itself for testing
11
PLL - fractionaL-n synthesizer - sMt
10 11 12
13
r/W
lkd_to_sdo_always
0
14 16:15 18:17 19
r/W r/W r/W r/W
lkd_ringosc_mono_select lkd_ringosc_cfg lkd_monost_duration lkd_ringosc_testmode
0 0 0 0
11 - 44
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 37. Reg 1Bh GPO Control Register
Bit Type gpo_sel gpo_sel<3:0> = 0000 Name Default 0 Description selects data to be driven on GPo ports GPo3 <=gposel_0_data<2> GPo2 <= gposel_0_data<1> GPo1 <= gposel_0_data<0> GPo3 <= xref_clk_in GPo2 <= ref_clk_in GPo1 <= vco_div_clkin GP03 <= pfd_up_in GP02 <= pfd_dn_in GP01 <= LKD_monost_window GP03 <= pfd_sat_ref_in GP02 <= pfd_sat_vco_div_in GP01 <= delta_integer_cycslip_sel, this strobe holds the gain of the PfD at max for anti-cycle slipping GP03 <= xref_clk_in GP02 <= xref_sin_in GP01 <= sd_frac_strobe_sync, internally synchronized frac strobe Vco serial Port Mirror GPo3 - VsDo GPo2 = VscK GPo1 = sVLe GP03 <= sD_intz1<1> GP02 <=sD_intz1<2> GP01 <= sD_intz1<3> 3-bit quantized version of the Vco phase GP03 <= aux_clk GP02 <= ringosc_test GP01 <= clk_sD GP03 <= 00 GP02 <= ramp_busy GP01 <= vcot_busy not used GP03 <= Quantizer output 3rd lsb GP02 <= Quantizer output 2nd lsb GP01 <= Quantizer output lsb this data is driven on gpo if gpo_sel==0 enables tri-state drivers on GPo output pads 0 0 reserved must write 0 on chip iD 478732 chip iD 481502 only 000 = all GPo pad drivers enabled xx1 = disable GPo1 pad driver x1x = disable GPo2 pad driver 1xx = disable GPo3 pad driver
gpo_sel<3:0> = 0001
gpo_sel<3:0> = 0010
gpo_sel<3:0> = 0011
11
PLL - fractionaL-n synthesizer - sMt
11 - 45
gpo_sel<3:0> = 0100 3:0 r/W gpo_sel<3:0> = 0101
gpo_sel<3:0> = 0110
gpo_sel<3:0> = 0111
gpo_sel<3:0> = 1000 gpo_sel<3:0> = 1001 gpo_sel<3:0> = 1010 6:4 7 r/W r/W gpo_sel_0_data gpo_dig_drive_en chip iD 478732 reserved chip iD 481502 gpo_ind_drive_dis
10:8
r/W
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 38. Reg 1Ch Phase Detector CSP Register
Bit Type Name Default Description 0= cycle slip Prevention (csP) disabled 3:0 r/W pfds_sat_deltan 5'd4 4-bit value to advance or retard phase detector in Vco cycles if it reaches 2pi , i.e. cycle slip prevention. 1st bit is polarity, enabled by rstb csP PfD flip-flops rstB: 1 - controlled by the pfds_rstb bit: 0 - auto-controlled by the csP logic forces the PfD into reset, which tristates charge pump, freezes charge on the loop filter, and hence opens the loop csP PfD ff rstb 1 - enables the cycle slip Prevention (csP) feature of the PfD
4
r/W
pfds_rstb_force
0
11
PLL - fractionaL-n synthesizer - sMt
5
r/W
pfds_rstb
1
Table 39. Reg 1Dh VCO Tune Port Control Register
Bit Type Name Default Description selects the source of control of the timing of the mid-rail voltage, voltage_force=0 selects autotune state machine voltage_force=1 selects voltage_enable from sPi Used for mid-rail control of Vco during autotuning forces mid-rail voltage on the charge pump output from the sPi when voltage_force=1 Used for mid-rail control of Vco during autotuning
0
r/W
voltage_force
0
1
r/W
voltage_enable
0
Table 40. Reg 1Eh Temperature Sensor Register
Bit 0 Type r/W Name tsens_spi_enable Default 0 Description enable the temperature sensor, draws ~2ma current, must strobe tsens_spi_strobe reg 00h <3>
Table 41. Reg 1Fh LD, VCO & Ramp Busy Read Only Register
Bit 0 3:1 4 5 Type ro ro ro ro ro_lock_detect ro_dsm_overflow ro_spi_vco_busy ro_ramp_busy Name Default 0 0 0 0 Description 1 = locked, 0 = unlocked 1 = modulator overflow set when Vco autotuning is running sweeper status flag, set when ramp is busy, cleared when at end of ramp or not used
Table 42. Reg 20h VCO Tune Caps Read Only Register (vcot)
Bit Type Name Default Description reads the values of the Vco switched resonator bank determined by the autotune routine (see ) 0 = max Vco freq 63 = min Vco freq
5:0
ro
vcot_caps
0
11 - 46
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
Table 43. Reg 21h Temperature Sensor Read Only Register
Bit Type Name Default Description current temperature from temp sensor lsb = 17.5c 0000111 = temp >= 82.5c 0000110 = temp 0000000 = temp <=-22.5c tsens_temperature = floor ((temp+40)/17.5)
6:0
ro
tsens_temperature
0
Table 44. Reg 22h Autotune Result Register
Bit 16:0 Type ro vcot_cnt Name Default 0 Description contains the results of the autotune counter can be used to calculate the Vco frequency and optimum Vco setting selected by the autotune
Outline Drawing
11
PLL - fractionaL-n synthesizer - sMt
11 - 47
notes: 1. PacKaGe BoDy MateriaL: LoW stress inJection MoLDeD PLastic siLica anD siLicon iMPreGnateD. 2. LeaD anD GroUnD PaDDLe MateriaL: coPPer aLLoy. 3. LeaD anD GroUnD PaDDLe PLatinG: 100% Matte tin. 4. DiMensions are in inches [MiLLiMeters]. 5. LeaD sPacinG toLerance is non-cUMULatiVe. 6. PaD BUrr LenGth shaLL Be 0.15mm MaX. PaD BUrr heiGht shaLL Be 0.25mm MaX. 7. PacKaGe WarP shaLL not eXceeD 0.05mm 8. aLL GroUnD LeaDs anD GroUnD PaDDLe MUst Be soLDereD to PcB rf GroUnD. 9. refer to hittite aPPLication note for sUGGesteD PcB LanD Pattern.
Package Information
Part number hMc702LP6ce Package Body Material rohs-compliant Low stress injection Molded Plastic Lead finish 100% matte sn MsL rating MsL1
[2]
Package Marking [1] h702 XXXX
[1] 4-Digit lot number XXXX [2] Max peak reflow temperature of 260 c
For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com

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